A key to continued CMOS miniaturization is the ability to scale down the horizontal and vertical dimensions of the semiconductor device while increasing speed, decreasing power, and operating at lower voltages. As devices are scaled below 0.25 .mu.m, the sheet resistance and contact resistance of the transistor contacts must be maintained at low values. A further requirement is that the source-to-substrate leakage be maintained low in order to ensure device and circuit performance without error. These requirements put stringent boundary conditions on the nature and dimension of the gate and source/drain contacts, which are typically composed of metal silicides in microprocessors, ASICS and DRAM devices. In order to obtain low sheet resistance, the silicides must have resistivities below 100 .mu.Ohm-cm and a thickness greater than 200 .ANG..
For self-aligned silicide processes, used ubiquitously for microprocessors and widely in DRAM technology, the silicide thickness must be minimized to avoid excessive consumption of silicon in the source/drain region. Excessive silicon consumption leads to silicide penetration of the junction and high leakage currents. This becomes more critical as the junction depth shrinks with devices having a channel length below 0.25 .mu.m. In addition, in order to maintain abrupt and shallow p-/n-junctions in scaled CMOS devices, the thermal annealing, which follows junction formation, must be reduced to minimize dopant motion in the junction.
In order to meet the above conflicting requirements, source/drain silicide materials having a balance of low resistivity and moderate silicon consumption are being used. Such material include Ti silicides, Co silicides and Ni silicides. Additionally, the trend in silicide formation, as with junction formation, is toward utilizing annealing processes which have shorter times and high temperatures and that use lamp-based thermal annealing wherein the silicide formation is accomplished in 10-60 seconds. This minimizes side reactions, such as oxidation, inversion of silicide where polysilicon may move to the top surface of the silicide, and breaking up silicide film into islands or agglomerates, that are generally associated with increased sheet resistance and junction leakage. However, even rapid thermal annealing (RTA) can lead to agglomeration and increased resistance. This restricts the thermal process window for the reaction of the metal films to form low resistance contacts before the films become unstable. The tendency to agglomerate also increases as the transistor line width shrinks, further narrowing the process window for low resistance and low leakage contacts.
Evolution of silicide processing began in the late 1970's when silicides were introduced into wide spread use in large-scaled integrated (LSI) devices. Silicide formation was obtained by annealing at high temperatures for minutes or, in some cases, for hours in a furnace containing a flowing gas. More recently, RTA processes have been employed. In RTA only the silicon wafer is substantially heated and for periods not exceeding 1-2 minutes. The wafer is rapidly ramped up to a hold temperature (typically greater than 30.degree. C./sec) and, thereafter, rapidly cooled.
There are several examples in the prior art of silicide formation on silicon wafers utilizing very rapid thermal annealing (&lt;1 sec). These examples include the use of laser annealing and electron beam annealing. The laser beam examples are further subdivided between excimer, Q-switched YAG, and Continuous Wave (CW) annealing. One of the earliest reports from Poate, et al., "Laser-induced reactions of platinum and other metal films with silicon", Appl. Phys. Lett. 33, (1978) p. 918, indicated formation of silicide in the 100 ns time scale by heating with a Nd--YAG laser and causing the metal/silicon mixture to melt and recrystallize into silicides under beam diameters of about 10 microns. Other studies involving excimer annealing using 30 ns pulse also melted the silicon substrate to form the silicide.
Numerous studies using CW annealing in the 100 microsecond time regime have shown silicide formation by solid state diffusion. Some examples of such studies include: T. Shibata, et al. "Metal Silicon Reactions Induced by CW Scanned Laser and Electron Beams", Electrochem. Soc.: SOLID-STATE SCIENCE AND TECHNOLOGY, 128, No. 3 (1981) p. 637; G. Bomchili, et al., "Formation Kinetics of MoSi.sub.2 induced by CW Scanned Laser Beam", Appl. Phys. Lett., 41 (1982), p. 46; and I. Ursu, et al., "Titanium Silicide Synthesis as an effect of CW CO.sub.2 Laser Irradiation", J. Appl. Phy., 66 (1989), p. 5635. Silicide formation using electron beam irradiation has also been reported by T. Shibita, et al., ibid.
All of the above annealing techniques employ small diameter beams ranging from tens of microns (CW laser) to a millimeter (excimer laser). Annealing over macroscopically large areas require beam rastering.
Despite the current state of the art, there is a continued need to develop new and improved silicide processes which do not have any of the problems mentioned with the prior art processes.